RF60 Datasheet, PDF (102/157 Pages) –

RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
25.5. External Interrupts
The INT0 and INT1 external interrupt sources are configurable as active high or low. They are edge sensi-
tive only, not level sensitive. These are not the same INT0 and INT1 as found on original 8051 architecture.
Each of the INT0 and INT1 can invoke interrupt on the rising edge, falling edge, or both edges of the
selected GPIO pins associated with the INT0 and INT1, respectively.
The single edge or double edge feature is controlled by the EDGE_INT0 and EDGE_INT1 bits in the
PORT_SET register. The edge polarity is defined in the PORT_INTCFG register.
INT0 and INT1 are assigned to Port pins as defined in the PORT_INTCFG register. Note that the corre-
sponding pending flag for INT0 or INT1 is not automatically cleared by the hardware when the CPU vec-
tors to the ISR. This is a departure from the original 8051 architecture where if external interrupts were
configured to be edge sensitive the corresponding interrupt flag was cleared by hardware upon the exit
from the ISR routine.
The detection of the edges of INT0 and INT1 sources is done by sampling the associated port inputs by the
internal system clock. Therefore, the edge detector will miss pulses shorter then 2 periods of the internal
system clock periods. Note that the internal system clock frequency is programmable and can be as low as
24MHz/128. It is up to the user to recognize possible external interrupt delays associated with sampling of
the INT0 and INT1 by the system clock at the current, user selected, clock frequency.
The INT1 and INT0 internal signals are also used as capture event signals for timer 3 and 2, respectively, if
they are running in capture mode.
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