RF60 Datasheet, PDF (77/157 Pages) –

RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
23.2. Reset
Reset circuitry allows the controller to be easily placed in a predefined default condition. There is only one
external reset source for the device, which is power on reset. It get invoked at two occasions:
1. Power is supplied to the device. This means connecting the power supply to disconnected device.
2. The device is waking up from a shutdown mode. The power supply was connected before, but the
device was put into the shutdown mode. When it is awaken the power is supplied internally to all the
device systems.
On entry to this reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFR) are initialized to their defined reset values
XDATA registers (XREG) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory is lost, since the power got cycled.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Device starts its boot sequence. See other sections for description of the boot sequence.
23.3. Chip Program Levels
The boot process starts by reading the NVM configuration bytes in the Factory region of NVM. The infor-
mation about the programmed level of the chip is read first and the boot process acts accordingly.
After boot, the program level of the chip can be read as NVM_BLOWN[2:0] field in the PROT0_CTRL
register.
From user point of view there are 3 program levels of the chip:
1. Factory .. blank part leaving the factory. The factory chip calibration is written into NVM. ROM and
NVM Factory region is not readable by the user. Part can be used with debugging chain for software
development and User load can be programmed to the part. Boot process initializes the part based on
the Factory settings.
2. User .. same as Factory (blank) part, but with the User region programmed with user code. The boot
process will initialize the part according to the Factory settings and then copies the User load to the
CODE/XDATA or IRAM based on the User load. The code is not automatically run. The part can be
used with IDE for further software development. The part is still opened for further NVM programming
and the user can add additional data to the User region in the NVM. Debugging of the loaded code is
possible.
This program level can be used two ways:
User programs the User code to check the load before finalizing the product.
Program most of the User code into the chip. Then the customer will add additional information
specific for each chip on his own.
3. Run .. mission mode part, fully programmed for use in the field. No further NVM programming possible,
no C2 interface access enabled, with the exception of special mode for retest. No possibility of IDE
debug. The boot process is the same as in the case of User part, but after the user load is copied from
NVM to RAM’s the boot loader executes a jump to RAM address 0x0000 and the user application is
executed. The C2 is not enabled in this mode with the retest exception, briefly described in this
document.
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