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HD66765 Datasheet, PDF (9/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays
HD66765
Block Function Description
System Interface
The HD66765 has five high-speed system interfaces: an 80-system 16-bit/8-bit bus, a 68-system 16-bit/8-
bit bus, and a serial peripheral (SPI: Serial Peripheral Interface port). The interface mode is selected by
the IM2-0 pins.
The HD66765 has three 16-bit registers: an index register (IR), a write data register (WDR), and a read
data register (RDR). The IR stores index information from the control registers and the GRAM. The
WDR temporarily stores data to be written into control registers and the GRAM, and the RDR
n temporarily stores data read from the GRAM. Data written into the GRAM from the MPU is first written
tio into the WDR and then is automatically written into the GRAM by internal operation. Data is read
through the RDR when reading from the GRAM, and the first read data is invalid and the second and the
a following data are normal. When a logic operation is performed inside of the HD66765 by using the
ific display data set in the GRAM and the data written from the MPU, the data read through the RDR is used.
Accordingly, the MPU does not need to read data twice nor to fetch the read data into the MPU. This
c enables high-speed processing.
e Execution time for instruction excluding oscillation start is 0 clock cycle and instructions can be written
p in succession.
y S Table 2 Register Selection (8/16 Parallel Interface)
inar 80-system Bus
lim WR
RD
0
1
e 1
0
Pr 0
1
68-system
Bus
R/W
RS
0
0
1
0
0
1
Operations
Writes indexes into IR
Reads internal status
Writes into control registers and GRAM through WDR
1
0
1
1
Reads from GRAM through RDR
Table 3 Register Selection (Serial Peripheral Interface)
Start bytes
R/W Bits RS Bits
0
0
1
0
0
1
1
1
Operations
Writes indexes into IR
Reads internal status
Writes into control registers and GRAM through WDR
Reads from GRAM through RDR
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