HD66765 Datasheet, PDF (37/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

HD66765
Serial Data Transfer
Setting the IM1 pin to the GND level and the IM2 pin to the Vcc level allows standard clock-
synchronized serial data (SPI) transfer, using the chip select line (CS*), serial transfer clock line (SCL),
serial input data (SDI), and serial output data (SDO). For a serial interface, the IM0/ID pin function uses
an ID pin. If the chip is set up for serial interface, the DB15-2 pins which are not used must be fixed at
Vcc or GND.
The HD66765 initiates serial data transfer by transferring the start byte at the falling edge of CS* input. It
ends serial data transfer at the rising edge of CS* input.
The HD66765 is selected when the 6-bit chip address in the start byte transferred from the transmitting
n _{device matches the 6-bit device identification code assigned to the HD66765. The HD66765, when}
tio ^{selected, receives the subsequent data string. The least significant bit of the identification code can be}
determined by the ID pin. The five upper bits must be 01110. Two different chip addresses must be
a _{assigned to a single HD66765 because the seventh bit of the start byte is used as a register select bit (RS):}
ific ^{that is, when RS = 0, data can be written to the index register or status can be read, and when RS = 1, an}
instruction can be issued or data can be written to or read from RAM. Read or write is selected according
c to the eighth bit of the start byte (R/W bit). The data is received when the R/W bit is 0, and is transmitted
e _{when the R/W bit is 1.}
p _{After receiving the start byte, the HD66765 receives or transmits the subsequent data byte-by-byte. The}
S _{data is transferred with the MSB first. All HD66765 instructions are 16 bits. Two bytes are received with}
y _{the MSB first (DB15 to 0), then the instructions are internally executed. After the start byte has been}
r _{received, the first byte is fetched internally as the upper eight bits of the instruction and the second byte is}
a _{fetched internally as the lower eight bits of the instruction.}
in _{Four bytes of RAM read data after the start byte are invalid. The HD66765 starts to read correct RAM}
lim ^{data from the fifth byte.}
e _{Table 18 Start Byte Format}
Pr _{Transfer Bit}
S
1
2
3
4
5
6
7
8
Start byte format
Transfer start Device ID code
RS R/W
0
1
1
1
0
ID
Note: ID bit is selected by the IM0/ID pin.
Table 19 RS and R/W Bit Function
RS R/W Function
0
0
Sets index register
0
1
Reads status
1
0
Writes instruction or RAM data
1
1
Reads instruction or RAM data
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