HD66765 Datasheet, PDF (44/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

HD66765
Window Address Function
When data is written to the on-chip GRAM, a window address-range which is specified by the horizontal
address register (start: HSA7-0, end: HEA7-0) or the vertical address register (start: VSA7-0, end:
VEA7-0) can be written to consecutively.
Data is written to addresses in the direction specified by the AM bit (increment/decrement). When image
data, etc. is being written, data can be written consecutively without thinking a data wrap by doing this.
The window must be specified to be within the GRAM address area described below. Addresses must be
set within the window address.
n _{[Restriction on window address-range settings]}
tio (horizontal direction) 00H ≤ HSA7-0 ≤ HEA7-0 ≤ 3FH
a _{(vertical direction) 00H ≤ VSA7-0 ≤ VEA7-0 ≤ AFH}
ific ^{[Restriction on address settings during the window address]}
c _{(RAM address) HSA5 to 0 ≤ AD7-0 ≤ HEA7-0}
pe ^{VSA7-0 ≤ AD15-8 ≤ VEA7-0}
S _{Note: In high-speed RAM-write mode, the lower two bits of the address must be set as shown below}
y according to the value of the ID0 bit.
ar ^{ID0=0: The lower two bits of the address must be set to 11.}
Prelimin ^{ID0=1: The lower two bits of the address must be set to 00.}
44