HD66765 Datasheet, PDF (25/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

Frame Cycle Control (R0Bh)
HD66765
R/W RS
W1
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 DIV1 DIV0 0 0 0 0 RTN3 RTN2 RTN1 RTN0
Figure 14 Frame Cycle Control Instruction
RTN3-0: Set the line retrace period (RTN3-0) to be added to raster-row cycles. The raster-row cycle
becomes longer according to the number of clocks set at RTN3-0.
n _{DIV1-0: Set the division ratio of clocks for internal operation (DIV1-0). Internal operations are driven by}
tio ^{clocks which are frequency divided according to the DIV1-0 setting. Frame frequency can be adjusted}
along with the line retrace period (RTN3-0). When changing the drive-duty cycle, adjust the frame
a frequency. For details, see the Frame Frequency Adjustment Function section.
ific ^{Table 10 RTN Bits and Clock Cycles}
ec _RTN3
Sp ⁰
0
ry ₀
a ₀
in _:
lim ¹
Pre ¹
RTN2
0
0
0
0
:
1
1
RTN1
0
0
1
1
:
1
1
RTN0
0
1
0
1
:
0
1
Line Retrace Period
(Clock Cycles)
0
1
2
3
:
14
15
Clock
Cycles per
Raster-row
25
26
27
28
:
39
40
Table 11 DIV Bits and Clock Frequency
DIV1
0
0
1
1
DIV0
0
1
0
1
Division Ratio
Internal Operation
Clock Frequency
1
fosc / 1
2
fosc / 2
4
fosc / 4
8
fosc / 8
* fosc = R-C oscillation frequency
25