HD66765 Datasheet, PDF (38/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

HD66765
a) Timing of Basic Data-Transfer through Clock-Synchronized Serial Bus Interface
Transfer start
CS*
(Input)
Transfer end
SCL
(Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SDI
tion ^(Input)
MSB
LSB
"0" "1" "1" "1"
"0"
ID
RS
RW
DB
15
DB
14
DB
13
DB
12
DB
11
DB DB
10 9
DB
8
DB
7
DB DB
65
DB
4
DB
3
DB
2
DB
1
DB
0
Device ID code
RS R/W
Start byte
Index register setting, instruction, RAM data write
ifica ^SDO
(Output)
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
c _{Status read, instruction read, RAM data read}
e _{b) Timing of Consecutive Data-Transfer through Clock-Synchronized Serial Bus Interface}
Sp _CS*
(Input)
ry _SCL
a _(Input)
1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 1718 19 20 21 22 23 24 25 26 2728 29 30 31 32
in _SDI
(Input)
lim ^Start
Start byte
Instruction 1: upper
eight bits
Instruction 1: lower
eight bits
Instruction 2: upper
eight bits
Instruction 1: execution
End
time
Pre ^{Note: The first byte after the start byte is always the upper eight bits.}
c) RAM-Data Read-Transfer Timing
CS*
(Input)
SCL
(Input)
SDI
(Input)
Start byte
RS = 1,
R/W = 1
SDO
(Output)
Start
Dummy
read 1
Dummy
read 2
Dummy
read 3
Dummy
read 4
Dummy
read 5
RAM read:
upper
eight bits
RAM read:
lower
eight bits
End
Note: Five bytes of the RAM read data after the start byte are invalid. The HD66765 starts
to read the correct RAM data from the sixth byte.
Figure 29 Procedure for Transfer on Clock-Synchronized Serial Bus Interface
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