HD66765 Datasheet, PDF (42/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

HD66765
High-Speed RAM Write in the Window Address
When a window address range is specified, RAM data which is in an optional window area can be
rewritten consecutively and quickly by inserting dummy write operations so that RAM access counts
become 4N as shown in the tables below.
Dummy write operations may have to be inserted as the first or last operations for a row of data,
depending on the horizontal window-address range specification bits (HSA1 to 0, HEA1 to 0). Number
of dummy write operations of a row must be 4N.
Table 21 Number of Dummy Write Operations in High-Speed RAM Write (HSA Bits)
n _{HSA1 HSA0}
tio ₀
0
a ₀
1
ific ¹
0
1
1
Number of Dummy Write Operations to
be Inserted at the Start of a Row
0
1
2
3
pec Table 22 Number of Dummy Write Operations in High-Speed RAM Write (HEA Bits)
S _{HEA1 HEA0}
ry ₀
0
a ₀
1
in ₁
0
lim ¹
1
Number of Dummy Write Operations to
be Inserted at the End of a Row
3
2
1
0
Pre ^{Each row of access must consist of 4 × N operations, including the dummy writes.}
Horizontal access count =
first dummy write count + write data count + last dummy write count = 4 × N
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