HD66765 Datasheet, PDF (24/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

HD66765
Table of common driver (HD66764) instructions
IDX2 IDX1 IDX0
000
DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BS2 BS1 BS0 BT3 BT2 BT1 BT0 0 DC1 DC0 AP1 AP0 SLP
001
0 0 0 0 0 0 0 0 0 0 VC2 VC1 VC0
010
0 VR3 VR2 VR1 VR0 0 CT6 CT5 CT4 CT3 CT2 CT1 CT0
011
n 1 0 0
tio ^{1 0 1}
a _{1 1 0}
0 0 D1 CMS SPT SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10
0 0 0 0 0 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10
0 0 0 0 0 SS27 SS26 SS125 SS24 SS23 SS22 SS21 SS20
0 0 0 0 0 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20
cific _{Instruction setting change}
Change the instruction bit setting
corresponding to the HD66765
e _{Transfer to the common driver must be executed immediately after setting up the instruction}
Sp _{Index set R0Ah}
y _{Instruction read}
inar _{TE = "0"}
NO
(During transfer)
elim YES (Transfer can be executed)
Pr ^{Common side index (IDX2 to 0) Specify the IDX2 to 0 in the HD66764}
TE = 1 (transfer start)
instruction including a changed instruction bit
Notes: 1. Transfer to the common driver must take place immediately after setting up the instruction.
2. The serial transfer period takes a maximum of 1/fosc x 18 clock cycles (sec).
3. Serial transfer cannot be executed in standby mode. If the chip enters standbymode during transfer,
the serial transfer is forcibly suspended. Transfer must be executed again because correct transfer is
not guaranteed in this situation.
4. Serial transfer can be forcibly suspended by writing TE = 0. Transfer must be executed again because
correct transfer is not guaranteed in this situation.
5. Do not enter standby mode during transfer or forcibly terminate transfer except in case of emergency.
Before executing, confirm that the transfer is completed.
Figure 13 Common Interface: Serial Transfer Sequence
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