HD66765 Datasheet, PDF (31/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

Read Data from GRAM (R22h)
HD66765
R/W RS
R1
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0 ^{RD RD RD RD RD RD RD RD RD RD RD RD}
11 10 9 8 7 6 5 4 3 2 1 0
Figure 23 Read Data from GRAM Instruction
RD11–0: Read 12-bit data from the GRAM. When the data is read to the microcomputer, the first-word
read immediately after the GRAM address setting is latched from the GRAM to the internal read-data
latch. The data on the data bus (DB11–0) becomes invalid and the second-word read is normal.
tion ^{When bit processing, such as a logical operation, is performed within the HD66765, only one read can be}
processed since the latched data in the first word is used.
ifica ^{Sets the I/D, AM, HSA/HEA, and}
VSA/VEA bits
ec _{Address: N set}
ry ^{Sp First word}
Dummy read (invalid data)
GRAM -> Read-data latch
Sets the I/D, AM, HSA/HEA, and
VSA/VEA bits
Address: N set
First word
Dummy read (invalid data)
GRAM -> Read-data latch
limina ^{Second word}
Read (data of address N)
Read-data latch -> DB11-0
Second word
Read (data of address N)
DB11-0 -> GRAM
Pre^{Address: M set}
Automatic address update: N + α
First word
Dummy read (invalid data)
GRAM -> Read-data latch
First word
Dummy read (invalid data)
GRAM -> Read-data latch
Second word
Read (data of address M)
Read-data latch -> DB11-0
Second word
Write (data of address N+ α)
DB11-0 -> GRAM
i) Data read to the microcomputer
ii) Logical operation processing in the HD66765
Figure 24 GRAM Read Sequence
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