HD66765 Datasheet, PDF (35/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

HD66765
Parallel Data Transfer
16-bit Bus Interface
Setting the IM2/1/0 (interface mode) to the GND/GND/GND level allows 68-system E-clock-
synchronized 16-bit parallel data transfer. Setting the IM2/1/0 to the GND/Vcc/GND level allows 80-
system 16-bit parallel data transfer. When the number of buses or the mounting area is limited, use an 8-
bit bus interface.
n _CSn*
CS*
tio ^A1
H8/2245 HWR*
RS
WR* ^HD66765
a (RD*)
(RD*)
ific ^D15-D0
DB15-DB0
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c _{Figure 26 Interface to 16-bit Microcomputer}
pe _{8-bit Bus Interface}
y ^S Setting the IM2/1/0 (interface mode) to the GND/GND/Vcc level allows 68-system E-clock-synchronized
r _{8-bit parallel data transfer using pins DB15–DB8. Setting the IM1/0 to the Vcc/Vcc level allows 80-}
a _{system 8-bit parallel data transfer. The 16-bit instructions and RAM data are divided into eight}
in ^{upper/lower bits and the transfer starts from the upper eight bits. Fix unused pins DB7–DB0 to the Vcc}
or GND level. Note that the upper bytes must also be written when the index register is written to.
relim^CSn*
CS*
P ^A1
RS
H8/2245 HWR*
WR* ^HD66765
(RD*)
(RD*)
D15-D8
DB15-DB8
8
DB7-0
8
GND
Figure 27 Interface to 8-bit Microcomputer
Note:
Transfer synchronization function for an 8-bit bus interface
The HD66765 supports the transfer synchronization function which resets the upper/lower
counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. Noise causing transfer
mismatch between the eight upper and lower bits can be corrected by a reset triggered by
consecutively writing a 00H instruction four times. The next transfer starts from the upper eight
bits. Executing synchronization function periodically can recover any runaway in the display
system.
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