HD66765 Datasheet, PDF (29/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

HD66765
RAM Write Data Mask (R20h)
R/W RS
W1
DB15
0
DB14
0
DB13
0
DB12
0
DB11
WM
11
DB10
WM
10
DB9
WM
9
DB8
WM
8
DB7
WM
7
DB6
WM
6
DB5
WM
5
DB4
WM
4
DB3
WM
3
DB2
WM
2
DB1
WM
1
DB0
WM
0
Figure 19 RAM Write Data Mask Instruction
WM11–0: In writing to the GRAM, these bits mask writing in a bit unit. When WM11 = 1, this bit
masks the write data of DB11 and does not write to the GRAM. Similarly, the WM10–0 bits mask the
n ^{write data of DB10–0 in a bit unit. When SWP = 1, the upper and lower bytes in the write data mask are}
tio ^{swapped. For details, see the Graphics Operation Function section.}
a _{RAM Address Set (R21h)}
ific R/W RS
c _{W 1}
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pe _{Figure 20 RAM Address Set Instruction}
y ^{S AD15–0: Initially set GRAM addresses to the address counter (AC). Once the GRAM data is written,}
r _{the AC is automatically updated according to the AM and I/D bit settings. This allows consecutive}
a _{accesses without resetting addresses. Once the GRAM data is read, the AC is not automatically updated.}
in ^{GRAM address setting is not allowed in the standby mode. Ensure that the address is set within the}
specified window address.
lim Table 13 GRAM Address Range in Eight-grayscale Mode
re AD14–AD0
P _{"0000"H–"0083"H}
GRAM Setting
Bitmap data for COM1
"0100"H–"0183"H
Bitmap data for COM2
"0200"H–"0283"H
Bitmap data for COM3
"0300"H–"0383"H
Bitmap data for COM4
:
:
"AC00"H–"AC83"H
Bitmap data for COM173
"AD00"H–"AD83"H
Bitmap data for COM174
"AE00"H–"AE83"H
Bitmap data for COM175
"AF00"H–"AF83"H
Bitmap data for COM176
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