HD66765 Datasheet, PDF (33/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

Table 17 Instruction List
Reg.
No.
IR
SR
R00h
R01h
Register Name
Index
Status read
Start oscillation
Device code read
Driver output control
R02h
R03h
LCD-driving-waveform
control
Power control 1
R04h Contrast control
R05h Entry mode
R06h Compare register
R07h Display control
R0Ah COM driver interface control
Upper Code
Lower Code
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
*
*
*
*
*
*
*
*
*
ID6 ID5 ID4 ID3 ID2 ID1 ID0 Sets the index register value.
Description
1
0
L7 L6 L5 L4 L3 L2 L1 L0
0
C6 C5 C4 C3 C2 C1 C0 Reads the driving raster-row position (L7-0) and contrast setting (C6-0).
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1 Starts the oscillation mode.
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
1 Reads 0765H.
0
1
0
0
0
0
0
0 CMS SGS 0
0
0 NL4 NL3 NL2 NL1 NL0 _{Sets the common driver shift direction (CMS), segment driver shift}
direction (SGS), and driving duty ratio (NL4-0).
0
1
0
0
0
0
0
0 B/C EOR 0
0 NW5 NW4 NW3 NW2 NW1 NW0 _{Sets the LCD drive AC waveform (B/C), EOR output (EOR), and the}
number of n-raster-rows (NW5-0) at C-pattern AC drive.
0
1
0 BS2 BS1 BS0 BT3 BT2 BT1 BT0 0 DC2 DC1 DC0 AP1 AP0 SLP STB _{Sets the standby mode (STB), LCD power on (AP1-0),}
sleep mode (SLP), boosting cycle (DC2-0),
boosting ouput multiplying factor (BT3-0), and LCD drive bias value
(BS2-0).
0
1
0
0
0
0 VR3 VR2 VR1 VR0 0 CT6 CT5 CT4 CT3 CT2 CT1 CT0 _{Sets the contrast adjustment (CT6-0) and regulator adjustment (VR3-0).}
0
1
0
0
0
0
0
0 HWM 0
0
0 I/D1 I/D0 AM LG2 LG1 LG0 _{Specifies the logical operation (LG2-0), AC counter mode (AM), increment/}
decrement mode (I/D1-0) and high-speed-write mode (HWM).
0
1
0
0
0
0
0
0
0
0 CP7 CP6 CP5 CP4 CP3 CP2 CP1 CP0 Sets the compare register (CP7-0).
0
1
0
0
0
0
0 VLE2 VLE1 SPT 0
0
0
0
0 REV D1 D0 _{Specifies display on (D1-0), reversed display (REV), ,screen division driving}
(SPT), and vertical scroll (VLE2-1).
0
1
0
0
0
0
0
0
0
TE
0
0
0
0
0 IDX2 IDX1 IDX0 Specifies the serial transfer enable (TE) and index for the COM transfer
1
1
0
0
0
0
0
0
0
TE
0
0
0
0
0 IDX2 IDX1 IDX0 instructions (IDX2-0).
R0Bh Frame cycle control
0
1
0
0
0
0
0
0 DIV1 DIV0 0
0
0
0 RTN3 RTN2 RTN1 RTN0 Sets the line retrace period (RTN3-0) and operating clock frequency-division ratio (DIV1-0)
R0Ch Power control 2
R11h Vertical scroll control
R14h 1st screen driving position
R15h 2nd screen driving position
R16h Horizontal RAM address position
R17h Vertical RAM address position
R20h RAM write data mask
R21h
R22h
R30h
R31h
R32h
R33h
R34h
R35h
R36h
R37h
RAM address set
Write data to GRAM
Write data from GRAM
Grayscale palette control (1)
Grayscale palette control (2)
Grayscale palette control (3)
Grayscale palette control (4)
Grayscale palette control (5)
Grayscale palette control (6)
Grayscale palette control (7)
Grayscale palette control (8)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0 VC2 VC1 VC0 Sets an adjustment factor for the Vci voltage (VC2-0).
0
1 VL27 VL26 VL25 VL24 VL23 VL22 VL21 VL20 VL17 VL16 VL15 VL14 VL13 VL12 VL11 VL10 Specifies the 1st-screen display-start raster-row (VL17-10) and 2nd-
screen display-start raster-row (VL27-20).
0
1 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 _{Sets 1st-screen driving start (SS17-10) and end (SE17-10).}
0
1 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20 _{Sets 2nd-screen driving start (SS27-20) and end (SE27-20).}
0
1 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 _{Sets the start (HSA7-0) and end (HEA7-0) of the horizontal RAM address range.}
0
1 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 _{Sets the start (VSA7-0) and end (VEA7-0) of the vertical RAM address range.}
0
1
0
0
0
0 WM WM WM9 WM8 WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0 _{Specifies write data mask (WM15-0) at RAM write.}
11 10
0
1
AD15-8 (upper)
AD7-0 (lower)
Initially sets the RAM address to the address counter (AC).
0
1
Write Data (upper)
Write Data (lower)
Write data to RAM.
1
1
Read Data (upper)
Read Data (lower)
Read data from RAM.
0
1
0
0
0 PK14 PK13 PK12 PK11 PK10 0
0
0 PK04 PK03 PK02 PK01 PK00 Specifies the Grayscale palette.
0
1
0
0
0 PK34 PK33 PK32 PK31 PK30 0
0
0 PK24 PK23 PK22 PK21 PK20 Specifies the Grayscale palette.
0
1
0
0
0 PK54 PK53 PK52 PK51 PK50 0
0
0 PK44 PK43 PK42 PK41 PK40 Specifies the Grayscale palette.
0
1
0
0
0 PK74 PK73 PK72 PK71 PK70 0
0
0 PK64 PK63 PK62 PK61 PK60 Specifies the Grayscale palette.
0
1
0
0
0 PK94 PK93 PK92 PK91 PK90 0
0
0 PK84 PK83 PK82 PK81 PK80 Specifies the Grayscale palette.
0
1
0
0
0 PK114 PK113 PK112 PK111 PK110 0
0
0 PK104 PK103 PK102 PK101 PK100 Specifies the Grayscale palette.
0
1
0
0
0 PK134 PK133 PK132 PK131 PK130 0
0
0 PK124 PK123 PK122 PK121 PK120 Specifies the Grayscale palette.
0
1
0
0
0 PK154 PK153 PK152 PK151 PK150 0
0
0 PK144 PK143 PK142 PK141 PK140 Specifies the Grayscale palette.
Note: 1. '*' means 'doesn't matter'.
2. After setting TE = 1, 18 (max.) clock cycles are required for a serial transfer to be completed. During that time, do not change the bits of instructions which are to be transferred.
3. High-speed write mode is available only for the RAM writing.
HITACHI
33
Execu-tion
Cycle
0
0
10 ms
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0