HD66765 Datasheet, PDF (55/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

HD66765
6. Read/Write mode 2: AM = 1, LG1–0 = 001/010/011
This mode is used when the data is vertically written at high speed by performing a logical operation
with the original data. It reads the display data (original data), which has already been written in the
GRAM, performs a logical operation with the write data sent from the microcomputer, and rewrites
the data to the GRAM. This mode can read the data during the same access-pulse width (68-system:
enabled high level, 80-system: RD* low level) as for the write operation since the read operation of
the original data does not latch the read data into the microcomputer and temporarily holds it in the
read-data latch. However, the bus cycle requires the same time as the read operation. The write-data
mask function (WM11–0) is also enabled in these operations. After writing, the address counter (AC)
automatically increments by 256, and automatically jumps to the upper-right edge (I/D = 1) or upper-
left edge (I/D = 0) following the I/D bit after it has reached the lower edge of the GRAM.
tion ^{Operation Examples:}
1) I/D = "1", AM = "1", LG2-0 = "001" (Logical OR)
a _{2) WM11—0 = "FF0"H}
ific ^{3) AC = "0000"H}
DB11
DB0
c _{Write-data mask: 1 1 1 1 1 1 1 1 0 0 0 0}
e _DB11
DB0
p _{Read data (1):}
100010010101
S _{Write data (1):}
101111000110
y _{Read data (2):}
000011110000
ar _{Write data (2):}
110000111000
Logical operation
(OR)
Logical operation
(OR)
101111010111
110011111000
limin ^"0000"H
Pre ^"0001"H
* * * * * * * * 0 1 1 1 Read data (1) + Write data (1)
* * * * * * * * 1 0 0 0 ^{Read data (2) + Write data (2)}
"AF00"H
GRAM
Note: 1. The bits in the GRAM indicated by ’*’ are not changed.
2. After writin to address "AF00"H, the AC jumps to "0001"H.
Figure 41 Writing Operation of Read/Write Mode 2
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