HD66765 Datasheet, PDF (19/71 Pages) Hitachi Semiconductor – 396-channel Segment Driver with Internal RAM for 4096-color Displays

HD66765
During no display, when AP1–0 = 00, the current consumption can be reduced by ending the operational
amplifier and step-up circuit operation.
VC2-0: Sets an adjustment factor for the Vci voltage (VC2-0).
SLP: When SLP = 1, the HD66765 enters the sleep mode, where the internal display operations are
halted except for the R-C oscillator, thus reducing current consumption. Only the following instructions
can be executed during the sleep mode.
Power control (BS2–0, BT3–0, DC2–0, AP1–0, SLP, and STB bits)
Common interface control (TE, IDX)
n _{During the sleep mode, the other GRAM data and instructions cannot be updated although they are}
tio ^retained.
a _{Note: BS2-0, BT3-0, DC2-0, AP1-0, VC2-0 and SLP bits are for setting the common driver. Control}
ific ^{according to the bits’ values is executed by the common driver. For details, see the data sheet for}
the common driver.
c _{STB: When STB = 1, the HD66765 enters the standby mode, where display operation completely stops,}
e _{halting all the internal operations including the internal R-C oscillator. Further, no external clock pulses}
p _{are supplied. For details, see the Standby Mode section.}
y ^{S Only the following instructions can be executed during the standby mode.}
ar a. Standby mode cancel (STB = 0)
in ^{b. Start oscillation}
lim ^{During the standby mode, the GRAM data and instructions may be lost. To prevent this, they must be set}
again after the standby mode is canceled. Serial transfer to the common driver is not possible when it is in
Pre ^{standby mode. Transfer the data again after it has been released from standby mode.}
Contrast Control (R04h)
R/W RS
W1
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 VR3 VR2 VR1 VR0 0 CT6 CT5 CT4 CT3 CT2 CT1 CT0
Figure 7 Contrast Control Instruction
CT6–0: These bits control the LCD drive voltage to adjust 128-step contrast. For details, see the Contrast
Adjuster section.
VR3–0: These bits adjust the output voltage in the LCD drive reference generator.
Note: CT6-0 and VR3-0 bits are for setting the common driver. Control according to the bits’ values is
executed by the common driver. For details, see the data sheet for the common driver.
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