HD404849 Datasheet, PDF (86/125 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

Transfer completion
(IFS1 ← 1)
Interrupts inhibited
IFS1 ^← 0
SM1A write
Yes
IFS1 = 1
No
Normal
termination
HD404849 Series
Transmit clock
error processing
Transmit clock error detection flowchart
State
Transmit clock
wait state
Transfer state
Transmit clock wait state
Transfer state
SCK pin
(input)
SMRA
write
IFS
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SMRA is written,
IFS is set.
Flag set because octal
counter reaches 000
Flag reset at
transfer completion
Transmit clock error detection procedures
Figure 69 Transmit Clock Error Detection
86