HD404849 Datasheet, PDF (11/125 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404849 Series
Bits in the interrupt control bits area and register flag area can be set and reset by the
SEM/SEMD and REM/REMD instructions, and tested with the TM/TMD instructions.
Other instructions have no effect on these bits. Note the following restrictions for each
bit.
IE
IM
LSON
IAOF
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
DTON
Not used
SEM/SEMD
Allowed
Not executed
Not executed
Allowed
Allowed
Not executed in active mode
Used in subactive mode
Not executed
REM/REMD
Allowed
Allowed
Allowed
Not executed
Inhibited
Allowed
Not executed
TM/TMD
Allowed
Allowed
Inhibited
Inhibited
Allowed
Allowed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST cannot be guaranteed.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
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