HD404849 Datasheet, PDF (23/125 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404849 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4 Interrupt Enable Flag (IE: $000, Bit 0)
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT₀, INT₁, INT₂, INT₃): There are four external interrupt signals.
External Interrupt Request Flags (IF0–IF3: $000, $001, $022): IF0 and IF1 are set when the signals
input to INT₀ and INT₁ are falling, and IF2 and IF3 are set when the signals input to INT₂ and INT₃ are
rising or falling, as listed in table 5. The INT₂ and INT₃ interrupt edges are selected by the detection edge
select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13.
Table 5 External Interrupt Request Flags (IF0–IF3: $000, $001, $022)
IF0–IF3
0
1
Interrupt Request
No
Yes
Detection edge selection register 1 (ESR1: $026)
Bit
Initial value
Read/Write
Bit name
3
0
W
ESR13
2
0
W
ESR12
1
0
W
ESR11
0
0
W
ESR10
ESR13 ESR12
0
0
1
1
0
1
INT₃ detection edge
No detection
Falling-edge detection
Rising-edge detection
Double-edge detection^*
ESR11 ESR10
0
0
1
1
0
1
INT₂ detection edge
No detection
Falling-edge detection
Rising-edge detection
Double-edge detection^*
Note: * Both falling and rising edges are detected.
Figure 12 Detection Edge Selection Register 1 (ESR1)
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