HD404849 Datasheet, PDF (102/125 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404849 Series
Table 30 LCD Frame Frequencies for Different Duty Cycles
Frame Frequencies
Duty Cycle LMR3 LMR2
f_OSC = 400 kHz f_OSC = 800 kHZ f_OSC = 2 MHz
Static
0
0
CL0 512 Hz
512 Hz
512 Hz
1
CL1 390.6 Hz
781.3 Hz
1953 Hz
1
0
CL2 48.8 Hz
97.7 Hz
244.1 Hz
1
CL3* 24.4 Hz
48.8 Hz
122.1 Hz
64 Hz
64 Hz
64 Hz
1/2
0
0
CL0 256 Hz
256 Hz
256 Hz
1
CL1 195.3 Hz
390.6 Hz
976.6 Hz
1
0
CL2 24.4 Hz
48.8 Hz
122.1 Hz
1
CL3* 12.2 Hz
24.4 Hz
61 Hz
32 Hz
32 Hz
32 Hz
1/3
0
0
CL0 170.7 Hz
170.7 Hz
170.7 Hz
1
CL1 130.2 Hz
260.4 Hz
651 Hz
1
0
CL2 16.3 Hz
32.6 Hz
81.4 Hz
1
CL3* 8.1 Hz
16.3 Hz
40.7 Hz
21.3 Hz
21.3 Hz
21.3 Hz
1/4
0
0
CL0 128 Hz
128 Hz
128 Hz
1
CL1 97.7 Hz
195.3 Hz
488.3 Hz
1
0
CL2 12.2 Hz
24.4 Hz
61 Hz
1
CL3* 6.1 Hz
12.2 Hz
30.5 Hz
16 Hz
16 Hz
16 Hz
Note: * The division ratio depends on the value of bit 3 of timer mode register A (TMA).
Upper value: When TMA3 = 0, CL3 = f_OSC × duty cycle/16384.
Lower value: When TMA3 = 1, CL3 = 32.768 kHz × duty cycle/512.
f_OSC = 4 MHz
512 Hz
3906 Hz
488.3 Hz
244.1 Hz
64 Hz
256 Hz
1953 Hz
244.1 Hz
122.1 Hz
32 Hz
170.7 Hz
1302 Hz
162.8 Hz
81.4 Hz
21.3 Hz
128 Hz
976.6 Hz
122.1 Hz
61 Hz
16 Hz
LCD Output Register 3 (LOR3: $01F): Write-only register used to specify ports R6 and R7 as pins
SEG13–SEG20 in 4-pin units (figure 88).
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