HD404849 Datasheet, PDF (82/125 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404849 Series
Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 67.
 STS wait state
 Transmit clock wait state
 Transfer state
 Continuous clock output state (only in internal clock mode)
• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 67). In STS
wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is
then executed (01, 11), the serial interface enters transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)
increments the octal counter, shifts the serial data register, and puts the serial interface in transfer state.
However, note that if clock continuous output mode is selected in internal clock mode, the serial
interface does not enter transfer state but enters clock continuous output state (17).
The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04,
14) in transmit clock wait state.
• Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge
of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction
sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is
executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait
state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode.
In internal clock mode, the transmit clock stops after outputting eight clocks.
In transfer state, writing data to serial mode register A (SMRA: $005) (06, 16) initializes the serial
interface, and STS wait state is entered.
If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 2) is set
by the octal counter that is reset to 000.
• Clock continuous output state (only in internal clock mode): Clock continuous output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the SCK pin.
When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters clock continuous output state.
If serial mode register A (SMRA: $005) is written to in clock continuous output mode (18), STS wait
state is entered.
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