HD404849 Datasheet, PDF (24/125 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

Detection edge selection register 2 (ESR2: $027)
Bit
Initial value
Read/Write
Bit name
3
0
W
ESR23
2
1
0
0
—
—
W
—
—
ESR22 Not used Not used
HD404849 Series
ESR23 ESR22
0
0
1
1
0
1
EVND detection edge
No detection
Falling-edge detection
Rising-edge detection
Double-edge detection^*
Note: * Both falling and rising edges are detected.
Figure 13 Detection Edge Selection Register 2 (ESR2)
External Interrupt Masks (IM0–IM3: $000, $001, $022): Prevent (mask) interrupt requests caused by
the corresponding external interrupt request flags, as listed in table 6.
Table 6 External Interrupt Masks (IM0–IM3: $000, $001, $022)
IM0–IM3
0
1
Interrupt Request
Enabled
Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.
Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA
0
1
Interrupt Request
No
Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the
timer A interrupt request flag, as listed in table 8.
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