HD404849 Datasheet, PDF (10/125 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404849 Series
Bit 3
IM0
0
(IM of INT₀)
Bit 2
IF0
(IF of INT₀)
Bit 1
RSP
(Reset SP bit)
1
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT₁)
Bit 0
IE
(Interrupt
enable flag)
IF1
(IF of INT₁)
$000
$001
2
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
$002
IMAD
3
(IM of A/D)
IFAD
(IF of A/D)
IMTD
(IM of timer D)
IFTD
(IF of timer D)
$003
(a) Interrupt control bits area
Bit 3
Bit 2
DTON
32 (Direct transfer
on flag)
ADSF
(A/D start flag)
RAME
33 (RAM enable
flag)
IAOF
(A/D current off
flag)
Bit 1
WDON
(Watchdog
on flag)
ICEF
(Input capture
error flag)
34
IM3
(IM of INT₃)
IMS
35 (IM of serial
interface)
IF3
(IF of INT₃)
IFS
(IF of serial
interface)
IM2
(IM of INT₂)
Not used
(b) Register flag area
Bit 0
LSON
(Low speed
on flag)
ICSF
(Input capture
status flag)
IF2
(IF of INT₂)
Not used
$020
$021
$022
$023
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
SP: Stack pointer
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
10