GS4911B Datasheet, PDF (97/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
Polarity
56h
15-10 Reserved. Set these bits to zero when writing to 56h. –
–
56h
9
AFS (GS4911B only)- set this bit HIGH to invert the
R/W
0
polarity of the AFS timing output signal.
By default, the AFS signal is HIGH for the duration of
the first line of the n’th video frame to indicate that the
ACLK dividers have been reset at the start of line 1 of
that frame.
NOTE: The GS4910B does not generate an AFS pulse
and will ignore the setting of this bit.
Reference: Table 1-3
56h
8
10FID - set this bit HIGH to invert the polarity of the
R/W
0
10FID timing output signal.
By default, the 10FID signal will go HIGH for one line at
the start of the 10-field sequence.
Reference: Table 1-3
56h
7
DE - set this bit HIGH to invert the polarity of the DE
R/W
0
timing output signal.
By default, the DE signal will be HIGH whenever pixel
information is to be displayed on the display device
Reference: Table 1-3
56h
6
Reserved. Set this bit to zero when writing to 56h.
–
–
56h
5
F_Digital - set this bit HIGH to invert the polarity of the F R/W
0
Digital timing output signal.
By default, the F Digital signal will be LOW for the entire
period of field 1.
Reference: Table 1-3
56h
4
F_Sync - set this bit HIGH to invert the polarity of the F R/W
0
Sync timing output signal.
By default, the F Sync signal will be HIGH for the entire
period of field 1.
Reference: Table 1-3
56h
3
V_Blanking - set this bit HIGH to invert the polarity of the R/W
0
V Blanking timing output signal.
By default, the V Blanking signal will be LOW for the
portion of the field/frame containing valid video data.
Reference: Table 1-3
36655 - 2 April 2006
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