GS4911B Datasheet, PDF (100/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
V_Stop_2
Operator_Polarity_2
H_Start_3
H_Stop_3
5Fh
15
Reserved. Set this bit to zero when writing to 5Fh.
–
–
5Fh
14-0
The value programmed in this register indicates the end R/W
0
line number of the trailing edge of the user-programmed
V Sync signal USER2_V. For interlaced output
standards, this value corresponds to the odd field line
number.
NOTE: The value programmed in this register must not
exceed the maximum number of lines per field of the
outgoing standard.
Reference: Section 3.8.3 on page 69
60h
15-4
Reserved. Set these bits to zero when writing to 60h. –
–
60h
3
Polarity_2 - Use this bit to invert the polarity of the final R/W
1
USER2 signal.
By default, the polarity of the user programmed signals
is active LOW. The polarity may be switched to active
HIGH by setting this bit LOW.
Reference: Section 3.8.3 on page 69
60h
2
AND_2 - logical operator: USER2_H AND USER2_V R/W
0
Set this bit HIGH to output a signal that is only active
when both USER2_H and USER2_V are active.
When this bit is HIGH, bit 1 and bit 0 of this register will
be ignored.
Reference: Section 3.8.3 on page 69
60h
1
OR_2 - logical operator: USER2_H OR USER2_V
R/W
0
Set this bit HIGH to output a signal that is active
whenever USER2_H or USER2_V are active.
When this bit is HIGH bit 0 of this register will be
ignored.
Reference: Section 3.8.3 on page 69
60h
0
XOR_2 - logical operator: USER2_H XOR USER2_V R/W
0
Set this bit HIGH to output a signal with the following
attributes: Signal becomes active when either
USER2_H or USER2_V is active. Signal is inactive
when USER2_H and USER2_V are both active or both
inactive.
Reference: Section 3.8.3 on page 69
61h
15-0
The value programmed in this register indicates the
R/W
0
pixel start point for the leading edge of the
user-programmed H Sync signal USER3_H.
NOTE: The value programmed in this register must be
less than the value programmed in H_Stop_3.
Reference: Section 3.8.3 on page 69
62h
15-0
The value programmed in this register indicates the
R/W
0
pixel end point for the trailing edge of the
user-programmed H Sync signal USER3_H.
NOTE: The value programmed in this register must not
exceed the maximum number of clock periods per line
of the outgoing standard.
Reference: Section 3.8.3 on page 69
36655 - 2 April 2006
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