GS4911B Datasheet, PDF (44/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

3.4.2 10FID
GS4911B/GS4910B Data Sheet
Timing for Graphics Formats
The GS4911B/GS4910B is pre-programmed to recognize the timing for 16
different graphics formats presented to the input reference pins. These graphic
formats are described in Section 1.4 on page 20.
The supported graphics standards are all progressive, and do not use the FSYNC
signal. Therefore, FSYNC should be held LOW by the application layer. The VESA
formats supported have a 0.5% frequency tolerance.
VSYNC transitions are typically co-timed with the leading edge of HSYNC. The
duration and polarity of these signals for each format is listed in Table 1-2.
NOTE: The user must ensure that the input HSYNC polarity for VID_STD [5:0] = 47
and 49 – 54 be active LOW.
The 10FID input is a reset pin, which can be used to reset the divider for the 10FID
output signal. In the GS4911B, the 10FID input pin will also reset the divider for the
AFS output signal. This default setting may be modified using the Audio_Control
register of the host interface (see Section 3.12.3 on page 79).
The GS4911B will reset the phase of the audio clocks to the leading edge of the H
Sync output on line 1 of every output frame in which the 10FID input is HIGH. This
enables the user to reset the phase of the dividers when generating custom signals
via the host interface (see Section 3.7.2.1 on page 65).
If the input reference format does not include a 10 Field ID signal, the external
10FID input pin should be held LOW.
The timing of the 10FID input signal is shown in Figure 3-5.
Total Line
10FID Input
Horizontal Sync Input
Line 1, Frame 1 every 'n' frames
Line 1 every n frames where:
n = 5 @ 29.97 fps, 30 fps
n = 10 @ 59.94 fps, 60 fps
Figure 3-5: 10FID Input Timing
36655 - 2 April 2006
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