GS4911B Datasheet, PDF (104/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
Ln_Count_Reset
83h
15
Toggle this bit to reset the line-based counters in the
R/W
0
device.
This is only required when locking the “f/1.001” HD
output standards to the 525-line SD input reference
standards, or vice-versa, AND:
1. The reference has been removed and subsequently
re-applied. In this case, the user should wait until the
reference has been re-detected by the device, which
may take up to 4 frames. See Section 3.5.3 on
page 47.
OR
2. The device is locked to blanking signals from a
deserializer, and the SDI input to the deserializer has
been switched upstream from the system. See
Section 3.6.5 on page 60.
83h
14-0
Reserved. Set these bits to zero when writing to 83h. –
–
36655 - 2 April 2006
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