GS4911B Datasheet, PDF (95/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
RSVD
Video_Control
VID_STD[5:0]
Clocks_Per_Line
Clocks_Per_Hsync
Hsync_To_SAV
Hsync_To_EAV
4Bh
–
Reserved.
–
–
4Ch
15-5
Reserved. Set these bits to zero when writing to 4Ch. –
–
4Ch
4
10FID_F_pulse - set this bit HIGH to stretch the 10FID R/W
0
pulse duration from 1 line to 1 field.
Reference: Section 3.8.1 on page 67
4Ch
3-2
Reserved. Set these bits to zero when writing to 4Ch. –
–
4Ch
1
Host_VID_STD - set this bit HIGH to select the output R/W
0
video standard using register 4Dh instead of the
external VID_STD[5:0] pins.
The external VID_STD[5:0] pins will be ignored, but
should not be left floating.
Reference: Section 1.4 on page 20
4Ch
0
Reserved. Set this bit to zero when writing to 4Ch.
–
–
4Dh
15-6
Reserved. Set these bits to zero when writing to 4Dh. –
–
4Dh
5-0
Replaces the external VID_STD[5:0] pins when
R/W
00h
VID_From_Host (bit 1 of address 4Ch) is HIGH.
Reference: Section 1.4 on page 20
4Eh
15-0
Contains the number of output video clock cycles per R/W
–
line for the selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference: Section 3.10 on page 74
4Fh
15-0
Contains the number of output video clock cycles in the R/W
–
active H Sync interval for the selected output timing
format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference: Section 3.10 on page 74
50h
15-0
Contains the number of output video clock cycles from R/W
–
the start of H Sync to the start of active video for the
selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference: Section 3.10 on page 74
51h
15-0
Contains the number of output video clock cycles from R/W
–
the start of H Sync to the end of active video for the
selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference: Section 3.10 on page 74
36655 - 2 April 2006
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