GS4911B Datasheet, PDF (15/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
41
TIMING_OUT_6
Synchronous Output
with PCLK1 ~
PCLK3
42
TIMING_OUT_7
Synchronous Output
with PCLK1 ~
PCLK3
43
TIMING_OUT_8
Synchronous Output
with PCLK1 ~
PCLK3
45
LVDS/PCLK3_VDD –
Power
Supply
Description
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See Section 1.5 on page 25 for signal descriptions.
NOTE: Default output is F digital.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See Section 1.5 on page 25 for signal descriptions.
NOTE: Default output is 10 Field ID (10FID).
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See Section 1.5 on page 25 for signal descriptions.
NOTE: Default output is Display Enable (DE).
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Most positive power supply connection for PCLK3 output circuitry and
LVDS driver. Connect to +1.8V DC.
36655 - 2 April 2006
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