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GS4911B Datasheet, PDF (73/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK
GS4911B/GS4910B Data Sheet
Example 2: Programming an output video clock of 74.175824MHz (74.25/1.001):
f--o---u---t
=
7----4---.-2---5- MHz
-1---.-0---0---1--------------
fin
27MHz
∴-N----v- = 7---4---2---5-----×-----1---0---0---0- = 2---5----0-
Dv 2700 × 1001 91
Therefore, program Nv = 250 and Dv = 91.
NOTE: The Nv and Dv values programmed in registers 20h-21h and 22h-23h are
not held until the custom video clock update bit (6) of register 16h is toggled.
3.9.2 Programming a Custom Audio Clock (GS4911B only)
The GS4911B’s audio clocks are derived from the fundamental audio sampling
frequency initially set by ASR_SEL[2:0]. At any time this fundamental sampling
frequency may be modified to create a custom output audio clock.
The user may generate any audio sampling frequency between 6.6kHz and 96kHz,
and therefore create a custom audio clock as high as 512*96kHz. When generating
a custom audio sampling frequency, ASR_SEL[2:0] must be set to 100b and bit 5
of register 31h (enable_384fs) must be kept LOW.
The fundamental sampling frequency is determined using a ratio based on the
27MHz reference. Therefore, to program a custom audio clock, the user must
calculate and program the set of integers (Na, Da) in the equation:
-N----a- = 1024 × --f-s--
Da
fin
where:
fs = desired fundamental audio sampling frequency
fin = 27MHz crystal reference
Na = numerator of the ratio (host register 33h-34h)
Da = denominator of the ratio (host register 35h-36h)
Before programming Na and Da, the numerator and denominator must be reduced
to their lowest factors.
For example, to program a fundamental audio sampling frequency of 42kHz:
-N----a- = 1024 × -----4---2---0---0---0------ = 4---3---0---0----8- = 1---7----9---2-
Da
27000000 27000 1125
Therefore, program Na = 1792 and Da = 1125 and toggle the custom audio clock
update bit (6) of register 31h. Using registers 3Fh to 41h, the custom audio
sampling frequency generated may then be multiplied by a factor of 64, 128, 256,
or 512 before being presented to the ACLK pins.
NOTE: The AFS reset described in Section 3.7.2 on page 63 will always remain
active.
36655 - 2 April 2006
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