GS4911B Datasheet, PDF (27/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
Table 1-3: Output Timing Signals (Continued)
Signal Name
Description
Default Output Pin
F Digital
10 Field Identification
Display Enable
F Digital is used in digital interlaced standards to indicate field 1 and field 2.
The F Digital changes state at the leading edge of every V Blanking pulse. It will
be LOW (default polarity) for the entire period of field 1 and for all lines in
progressive scan systems. It will be HIGH for all lines in field 2 .
The width and timing of this signal will be determined by the timing parameters
of the selected video standard (see Table 1-2), or according to custom
parameters programmed in the host interface (see Section 3.10 on page 74).
When in Genlock mode, the output F Digital signal will be phase locked to the
reference FSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on
page 37).
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.12.3 on page 79).
TIMING_OUT_6
The 10 Field Identification (10FID) signal is used to indicate the 10-field
sequence for 29.97Hz, 30Hz, 59.94Hz and 60Hz video standards. It will be
LOW for output standards with other frame rates.
TIMING_OUT_7
The sequence defines the phase relationship between film frames and video
frames, so that cadence may be maintained in mixed format environments.
The 10FID signal will be HIGH (default polarity) for one line at the start of the
10-field sequence. It will be LOW for all other lines. The signal’s rising and
falling edges will be simultaneous with the leading edge of the H Sync output
signal.
Alternatively, by setting bit 4 of the Video_Control register (see Section 3.12.3
on page 79), the 10FID output signal may be configured to go HIGH (default
polarity) on the leading edge of the H Sync output on line 1 of the first field in
the 10 field sequence, and be reset LOW on the leading edge of the H Sync
pulse of the first line of the second field in the 10 field sequence.
When in Genlock mode, the output 10FID signal will be phase locked to the
10FID reference input. If a 10FID input is not provided to the device, the user
must configure the 10FID output using register 1Ah of the host interface (see
Section 3.8.1 on page 67).
For applications involving audio, this signal may be used in place of the AFS
signal if the format selected is appropriate for a 10 field AFS repetition rate, and
the desired phase relationship of audio to video clock phasing coincides with
the desired film frame cadence.
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.12.3 on page 79).
Please see Section 3.8.1 on page 67 for more detail on the 10FID output signal.
The Display Enable (DE) signal is used to indicate the display enable for
graphic display interfaces.
This signal will be HIGH (default polarity) whenever pixel information is to be
displayed on the display device (i.e. whenever both H Blanking and V Blanking
are in the active video state)
The width and timing of this signal will be determined by the timing parameters
of the selected video standard (see Table 1-2), or according to custom timing
parameters programmed in the host interface (see Section 3.10 on page 74).
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.12.3 on page 79).
TIMING_OUT_8
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