GS4911B Datasheet, PDF (102/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
H_Start_4
H_Stop_4
V_Start_4
V_Stop_4
66h
15-0
The value programmed in this register indicates the
R/W
0
pixel start point for the leading edge of the
user-programmed H Sync signal USER4_H.
NOTE: The value programmed in this register must be
less than the value programmed in H_Stop_4.
Reference: Section 3.8.3
67h
15-0
The value programmed in this register indicates the
R/W
0
pixel end point for the trailing edge of the
user-programmed H Sync signal USER4_H.
NOTE: The value programmed in this register must not
exceed the maximum number of clock periods per line
of the outgoing standard.
Reference: Section 3.8.3 on page 69
68h
15
Reserved. Set this bit to zero when writing to 68h.
–
–
68h
14-0
The value programmed in this register indicates the start R/W
0
line number of the leading edge of the
user-programmed V Sync signal USER4_V. For
interlaced output standards, this value corresponds to
the odd field line number.
NOTE: The value programmed in this register must be
less than the value programmed in V_Stop_4.
Reference: Section 3.8.3 on page 69
69h
15
Reserved. Set this bit to zero when writing to 69h.
–
–
69h
14-0
The value programmed in this register indicates the end R/W
0
line number of the trailing edge of the user-programmed
V Sync signal USER4_V. For interlaced output
standards, this value corresponds to the odd field line
number.
NOTE: The value programmed in this register must not
exceed the maximum number of lines per field of the
outgoing standard.
Reference: Section 3.8.3 on page 69
36655 - 2 April 2006
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