GS4911B Datasheet, PDF (47/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
Table 3-2: Ambiguous Standard Identification
Number Standard
H
(27MHz
Clocks)
16_H
(27MHz
Clocks)
V (lines) F (lines) Amb_Std_Sel[10:0]
1
1920x1080/60/2:1 interlace
800
12800
562.5
1125
XXXXXXXXX00
1920x1080/30/PsF
800
12800
562.5
1125
XXXXXXXXX01
1920x1035/60/2:1 interlace
800
12800
562.5
1125
XXXXXXXXX10
2
1920x1080/59.94/2:1 interlace
800.8
12813
562.5
1125
XXXXXXX00XX
1920x1080/29.97/PsF
800.8
12813
562.5
1125
XXXXXXX01XX
1920x1035/59.94/2:1 interlace
800.8
12813
562.5
1125
XXXXXXX10XX
3
1920x1080/50/2:1 interlace
960
15360
562.4
1125
XXXXX00XXXX
1920x1080/25/PsF
960
15360
562.4
1125
XXXXX01XXXX
4
601 525 / 2:1 interlace
1716
27456
262.5
525
XXX00XXXXXX
720x486/59.94/2:1 interlace
1716
27456
262.5
525
XXX01XXXXXX
4fsc 525 / 2:1 interlace
1716
27456
262.5
525
XXX10XXXXXX
601 - 18MHz 525/2:1 interlace
1716
27456
262.5
525
XXX11XXXXXX
5
601 625 / 2:1 interlace
1728
27648
312.5
625
X00XXXXXXXX
720x576/50/2:1 interlace
1728
27648
312.5
625
X01XXXXXXXX
Composite PAL 625/2:1/25
1728
27648
312.5
625
X10XXXXXXXX
601 - 18MHz 625/2:1 interlace
1728
27648
312.5
625
X11XXXXXXXX
6
640 x 480 VGA @ 60Hz
857.14
13714
525
525
0XXXXXXXXXX
720x483/59.94/1:1 progressive
858
13728
525
525
1XXXXXXXXXX
NOTE: ‘X’ signifies ‘don’t care.’ The X bit will be ignored when determining which standard to select in each of the 6 groups above.
3.5.3 Behaviour on Loss and Re-acquisition of the Reference Signal
By default, the GS4911B/GS4910B will ignore one missing H pulse on the HSYNC
pin and will continue to operate in Genlock mode (although the LOCK_LOST pin
will temporarily be set HIGH). This behaviour is controlled by the Run_Window bits
of register address 24h.
If there are two consecutive missing H pulses on the HSYNC input pin, the
REF_LOST and LOCK_LOST pins will both go HIGH and the device will enter
Freeze mode. An internal flywheel ensures the selected output clock and timing
signals maintain their previous phase and frequency and continue to operate
without glitches.
The VSYNC and FSYNC signals are not monitored in Genlock mode; loss of signal
on these pins will not affect the operation of the device.
NOTE 1: If the input reference is removed and re-applied, all line-based timing
outputs will be inaccurate for up to one frame for all output standards.
36655 - 2 April 2006
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