GS4911B Datasheet, PDF (90/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
Audio_Control
(GS4911B only)
ASR_SEL[2:0]
(GS4911B only)
31h
15-10 Reserved. Set these bits to zero when writing to 31h. –
–
31h
9-7
AFS_Reset_Window - These bits may be used to adjust R/W
010b
the value by which the audio clock counters are allowed
to drift from the output AFS pulse.
The encoding scheme for this register is shown in
Table 3-9.
NOTE: The default setting of this register will provide a
reset window that is sufficient for most standards. To
maintain correct audio clock frequencies for some
VESA standards, the reset window may have to be
increased from its default setting. In this case, set the
value of this register to 1XX. See Table 3-9.
Reference: Section 3.7.2 on page 63
31h
6
Update_Custom_A_Clock - this bit is used to update the R/W
0
custom audio clock parameters programmed in
registers 33h to 36h of the host interface. All non-zero
parameters in these registers will be updated via a LOW
to HIGH transition on this bit.
31h
5
Enable_384fs - set this bit HIGH to enable the 384fs
R/W
0
and 192fs audio clock outputs. This must be set in
addition to registers 3Fh to 41h.
NOTE: If this bit is HIGH, then a 512fs audio clock will
have a 33% duty cycle when fs = 96kHz.
Reference: Section 3.7.2 on page 63
31h
4-3
Reserved. Set these bits to zero when writing to 31h. –
–
31h
2
Host_ASR_SEL - set this bit HIGH to select the audio R/W
0
sample rate using register 32h instead of the external
ASR_SEL[2:0] pins.
The external ASR_SEL[2:0] pins will be ignored, but
should not be left floating.
Reference: Section 3.7.2 on page 63
31h
1
AFS_F_Pulse - set this bit to 1 to stretch the AFS pulse R/W
0
duration from 1 line to 1 field.
Reference: Section 3.8.2 on page 68
31h
0
AFS_Reset_Disable - set this bit HIGH to disable the R/W
0
10FID input reference pin from resetting the output AFS
pulse. If this bit is set HIGH, the output AFS pulse will
free-run or may be reset using register 1Ah. The
external 10FID pin should not be left floating.
Reference: Section 3.8.2 on page 68
32h
15-3
Reserved. Set these bits to zero when writing to 32h. –
–
32h
2-0
Replaces the external ASR_SEL[2:0] pins when
R/W
011b
Host_ASR_Select (bit 2 of address 31h) is HIGH.
The default setting of this register corresponds to an
audio sample rate of 48kHz.
Reference: Section 3.7.2 on page 63
36655 - 2 April 2006
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