GS4911B Datasheet, PDF (89/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
PCLK2_Phase/Divide
PCLK3_Phase/Divide
PCLK3_Tristate
RSVD
2Dh
15-7
Reserved. Set these bits to zero when writing to 2Dh. –
–
2Dh
6
Current_P2 - selects the current drive capability of the R/W
0
PCLK2 pin. Set this bit HIGH for high current drive.
Otherwise, the current drive will be low.
NOTE: The current drive should be set high if PCLK2 is
greater than 100MHz.
Reference: Section 3.7.1 on page 61
2Dh
5-2
PCLK2_Phase - adjusts the output phase of the PCLK2 R/W
0
clock with respect to the timing output pins. Phase is
delayed in 700ps (nominal) increments as shown in
Table 3-6.
Reference: Section 3.7.1 on page 61
2Dh
1
Divide_By_4 - set this bit HIGH to divide the output
R/W
0
PCLK2 by four.
NOTE: Setting this bit and bit 0 simultaneously HIGH
will hold the PCLK2 pin LOW.
Reference: Section 3.7.1 on page 61
2Dh
0
Divide_By_2 - set this bit HIGH to divide the output
R/W
0
PCLK2 by two.
NOTE: Setting this bit and bit 1 simultaneously HIGH
will hold the PCLK2 pin LOW.
Reference: Section 3.7.1 on page 61
2Eh
15-6
Reserved. Set these bits to zero when writing to 2Eh. –
–
2Eh
5-2
PCLK3_Phase - adjusts the output phase of the
R/W
0
PCLK3/PCLK3 clock with respect to the timing output
pins. Phase is delayed in 700ps (nominal) increments
as shown in Table 3-6.
Reference: Section 3.7.1 on page 61
2Eh
1
Divide_By_4 - set this bit HIGH to divide the output
R/W
0
PCLK3/PCLK3 by four.
Setting this bit and bit 0 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference: Section 3.7.1 on page 61
2Eh
0
Divide_By_2 - set this bit HIGH to divide the output
R/W
0
PCLK3/PCLK3 by two.
Setting this bit and bit 1 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference: Section 3.7.1 on page 61
2Fh
15-2
Reserved. Set these bits to zero when writing to 2Fh. –
–
2Fh
1-0
Set these bits to 11b to tristate the PCLK3 / PCLK3 pins. R/W
00b
Reference: Section 3.7.1 on page 61
2Fh - 30h –
Reserved.
–
–
36655 - 2 April 2006
89 of 113