GS4911B Datasheet, PDF (55/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
where:
f_out = output video clock frequency
f_Href = reference H pulse frequency on HSYNC
H_Feedback_Divide = numerator of the divide ratio (host register 28h-29h)
H_Reference_Divide = denominator of the divide ratio (host register 2Ah-2Bh)
Before programming H_Feedback_Divide and H_Reference_Divide, the
numerator and denominator must be reduced to their lowest factors.
For example, to manually genlock an output format with a 74.25MHz video clock to
a reference with a 27MHz video clock and 1716 clocks per line, the following
calculations are necessary:
f_Href
=
---2---7----- M H z
1716
∴-^H----^_---^F----^e---^e--^d---^b---^a---^c---^k---^_---^D----ⁱ--^v--ⁱ--^d---^e- = ^{7----4---.-2---5---M}------^H----^z- = 74.25 × ^{1---7---1----6-} = ^{1---2---7---4---1---3--}= ^{4---7---1---9--}
H_Reference_Divide _{---2---7-----MHz}
27
27
1
1716
Therefore, program H_Feedback_Divide = 4719 and H_Reference_Divide = 1.
Output Line/Frame Reset Host Registers
In addition to programming H_Feedback_Divide and H_Reference_Divide, the
user must also define the ratio of the output frame rate to the reference frame rate.
The denominator of this ratio is programmed in the Output_FV_Reset register at
address 18h of the host interface. Before Output_FV_Reset is programmed, the
numerator and denominator must be reduced to their lowest factors. Two
examples are demonstrated below:
Example 1: the reference has a frame rate of 30Hz and the output frame rate is
50Hz:
O_-----u_---t_--p_---u_---t_---F_---r_---a_---m_----e_----R_----a_---t_--e_{- =} 5---0--₌ 5--
Input Frame Rate 30 3
Therefore, program Output_FV_Reset = 3. The numerator does not have to be
programmed.
Example 2: the reference has a frame rate of 29.97Hz and the output frame rate is
50Hz:
O_-----u_---t_-p_---u_----t_---F_---r_---a_---m_----e_----R_----a_---t_--e_{- = ----5---0----- =} 1---0----0--1--
Input Frame Rate 29.97 600
Therefore, program Output_FV_Reset = 600. The numerator does not have to be
programmed.
Additionally, the Frame_Divider_Reset register (address19h) must be configured
to initialize the counter reset programmed in register 18h.
36655 - 2 April 2006
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