GS4911B Datasheet, PDF (39/113 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

GS4911B/GS4910B Data Sheet
2. For both sync and blanking-based input references, the device will advance all
line-based output timing signals by 1 line relative to the input VSYNC
reference for all output standards except VID_STD[5:0] = 4, 6, and 8. This will
occur even when the V_Offset register is not programmed. The user may
compensate for this advance by adding 1 line to the desired vertical offset
before loading this value into the register.
3. When locking the "f/1.001" HD output standards to the 525-line SD input
reference standards, or vice versa, the device will delay all line-based output
timing signals by ΔVSync lines relative to the input VSYNC reference. This will
occur even when the V_Offset register is not programmed. The user may
compensate for this delay by subtracting ΔVSync lines from the desired
vertical offset before loading this value into the register.
The value ΔVSync is given by the equation:
ΔVSync = HSYNC_IN_Period + ΔVSYNC_HSYNC – (2 × HSYNC_OUT_Period )
where:
HSYNC_IN_Period = the period of the H reference pulse
ΔVSYNC_HSYNC = the time difference between the leading edges of the
applied V and H reference pulses
Hsync_OUT_Period = the period of the generated H Sync output
See Figure 3-1. H_Feedback_Divide represents the numerator of the ratio of
the output clock frequency to the frequency of the H reference pulse. It is
calculated as described in Section 3.6.2.1 on page 54.
HSYNC
HSYNC_IN_Period
VSYNC
H Sync
Δ VSYNC_HSYNC
HSync_OUT_Period
V Sync
Δ VSync
Figure 3-1: HD-SD Calculation
36655 - 2 April 2006
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