MC68HC705C9A Datasheet, PDF (99/118 Pages) Motorola, Inc – Microcontrollers

12.8 3.3-Vdc Control Timing
3.3-Vdc Control Timing
Characteristic⁽¹⁾
Symbol
Min
Max
Unit
Frequency of operation
Crystal
External clock
f_OSC
—
DC
2.0
MHz
2.0
Internal operating frequency (f_OSC ÷ 2)
Crystal
External clock
f_OP
—
DC
1.0
MHz
1.0
Cycle time
Crystal oscillator startup time
Stop recovery startup time (crystal oscillator)
t_CYC
t_OXOV
t_ILCH
1000
—
—
—
ns
100
ms
100
ms
RESET pulse width
t_RL
1.5
—
t_CYC
Timer
Resolution⁽²⁾
Input capture pulse width
Input capture pulse period
Interrupt pulse width low (edge-triggered)
t_RESL
4.0
t_TH, t_TL
125
t_TLTL
(3)
t_ILIH
250
—
t_CYC
—
ns
—
t_CYC
—
ns
Interrupt pulse period
t_ILIL
(4)
—
t_CYC
OSC1 pulse width
t_OH,t_OL
200
—
ns
1. V_DD = 3.3Vdc ± 0.3 Vdc, V_SS = 0 Vdc, T_A = –40 to +85°C, unless otherwise noted
2. Because a 2-bit prescaler in the timer must count four internal cycles (t_CYC), this is the limiting minimum factor in determining
the timer resolution.
3. The minimum period t_TLTL should not be less than the number of cycle times it takes to execute the capture interrupt service
routine plus 24 t_CYC.
4. The minimum t_ILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus
19 t_CYC.
t_TLTL*
t_TH*
t_TL*
TCAP PIN
* Refer to timer resolution data in 12.7 5.0-Vdc Control Timing and 12.8 3.3-Vdc Control Timing.
Figure 12-4. TCAP Timing Relationships
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
99