MC68HC705C9A Datasheet, PDF (36/118 Pages) Motorola, Inc – Microcontrollers

Interrupts
Function
Reset
Software
interrupt
(SWI)
External
interrupt
Timer
interrupts
SCI
interrupts
SPI
interrupts
Table 4-1. Vector Addresses for Interrupts and Resets
Source
Power-on reset
RESET pin
COP watchdog
Local Mask Global Mask
Priority
(1 = Highest)
None
None
1
User code
None
None
Same priority
as instruction
IRQ pin port B pins
None
I bit
2
ICF bit
ICIE bit
OCF bit
OCIE bit
I bit
3
TOF bit
TOIE bit
TDRE bit
TC bit
TCIE bit
RDRF bit
I bit
4
RIE bit
OR bit
IDLE bit
ILIE bit
SPIF bit
SPIE
I bit
5
MODF bit
Vector
Address
$3FFE–$3FFF
$3FFC–$3FFD
$3FFA–$3FFB
$3FF8–$3FF9
$3FF6–$3FF7
$3FF4–$3FF5
4.3 External Interrupt (IRQ or Port B)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled.
Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge
of IRQ. It is then synchronized internally and serviced as specified by the contents of $3FFA and $3FFB.
When any of the port B pullups are enabled, each pin becomes an additional external interrupt source
which is executed identically to the IRQ pin. Port B interrupts follow the same edge/edge-level selection
as the IRQ pin. The branch instructions BIL and BIH also respond to the port B interrupts in the same way
as the IRQ pin. See 7.3 Port B.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-only trigger operation is
selectable. In MC68HC05C9A mode, the sensitivity is software controlled by the IRQ bit in the C9A option
register ($3FDF). In the MC68HC05C12A mode, the sensitivity is determined by the C12IRQ bit in the
C12 mask option register ($3FF1).
NOTE
The internal interrupt latch is cleared in the first part of the interrupt service
routine; therefore, one external interrupt pulse can be latched and serviced
as soon as the I bit is cleared.
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
36
Freescale Semiconductor