MC68HC705C9A Datasheet, PDF (77/118 Pages) Motorola, Inc – Microcontrollers

SPI Registers
Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by a write to
the SPCR. Control bits SPE and MSTR may be restored by user software to their original state during
this clearing sequence or after the MODF bit has been cleared. When configured as an
MC68HC05C9A, it is also necessary to restore DDRD after a mode fault.
Bits 5 and 3–0 — Not Implemented
These bits always read 0.
10.5.3 Serial Peripheral Data I/O Register
The serial peripheral data I/O register (SPDR), shown in Figure 10-6, is used to transmit and receive data
on the serial bus. Only a write to this register will initiate transmission/reception of another byte and this
will only occur in the master device. At the completion of transmitting a byte of data, the SPIF status bit is
set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF
must be cleared by the time a second transfer of the data from the shift register to the read buffer is
initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and places data directly into the shift
register for transmission.
$000C
Read:
Write:
Reset:
Bit 7
SPD7
6
5
4
3
2
SPD6
SPD5
SPD4
SPD3
SPD2
Unaffected by reset
Figure 10-6. PI Data Register (SPDR)
1
SPD1
Bit 0
SPD0
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
77