MC68HC705C9A Datasheet, PDF (105/118 Pages) Motorola, Inc – Microcontrollers

SS
(INPUT)
SCK (CPOL = 0)
(INPUT)
SCK (CPOL = 1)
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
3.3- Vdc Serial Peirpheral Interface Timing
1
4
2
5
8
SLAVE MSB OUT
6
7
MSB IN
13
5
4
12
BIT 6–1
10
11
BIT 6–1
12
3
13
SLAVE LSB OUT
11
LSB IN
9
NOTE
Note:
Not defined but normally MSB of character just received.
a) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
SCK (CPOL = 0)
(INPUT)
SCK (CPOL = 1)
(INPUT)
8
MISO
(OUTPUT)
MOSI
(INPUT)
2
NOTE
1
5
4
5
4
10
SLAVE MSB OUT
6
7
MSB IN
13
12
BIT 6–1
10
11
BIT 6–1
12
3
13
9
SLAVE LSB OUT
LSB IN
Note:
Not defined but normally LSB of character previously transmitted.
b) SPI Slave Timing (CPHA = 1)
Figure 12-10. SPI Slave Timing Diagram
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
105