MC68HC705C9A Datasheet, PDF (40/118 Pages) Motorola, Inc – Microcontrollers

Resets
VDD
tVDDR
OSC12
INTERNAL
CLOCK1
INTERNAL
ADDRESS
BUS1
INTERNAL
DATA
BUS1
RESET
(C9A)
4064tCYC
tCYC
3FFE 3FFF
NEW
PC
NEW
PC
NEW
PCH
NEW _DUMMY OP
PCL
CODE
4
3FFE
3FFE
3FFE
3FFE
3FFF
NEW
PC
NEW
PC
tRL
3
PCH
PCL
DUMMY ^OP
CODe
RESET
(C12A)
tRL
3
Notes:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only meant to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
4. RESET outputs V_OL during 4064 power-on reset cycles when in C9A mode only.
Figure 5-2. Power-On Reset and RESET
5.4 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature which guards against program run-away failures. A timeout
of the computer operating properly (COP) timer generates a COP reset. The COP watchdog is a software
error detection system that automatically times out and resets the MCU if not cleared periodically by a
program sequence.
This device includes two COP types, one for C12A compatibility and the other for C9A compatibility. When
configured as a C9A the COP can be enabled by user software by setting COPE in the C9A COP control
register (C9ACOPCR). When configured as a C12A, the COP is enabled prior to operation by
programming the C12COPE bit in the C12A mask option register (C12MOR). The function and control of
both COPs is detailed below.
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
40
Freescale Semiconductor