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MC68HC705C9A Datasheet, PDF (102/118 Pages) Motorola, Inc – Microcontrollers
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Electrical Specifications
12.9 5.0-Vdc Serial Peripheral Interface Timing
No.
Characteristic(1)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
0.5
fOP
dc
2.1
MHz
Cycle time
1
Master
Slave
tCYC(M)
tCYC(S)
2.0
—
tCYC
480
—
ns
Enable lead time
2
Master
Slave
tLEAD(M)
tLEAD(S)
(2)
—
ns
240
—
Enable lag time
3
Master
Slave
tLAG(M)
tLAG(S)
(2)
—
ns
720
—
Clock (SCK) high time
4
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
ns
—
Clock (SCK) low time
5
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
ns
—
Data setup time (inputs)
6
Master
Slave
tSU(M)
tSU(S)
100
—
ns
100
—
Data hold time (inputs)
7
Master
Slave
8
Slave access time (time to data active from
high-impedance state)
tH(M)
tH(S)
tA
100
—
ns
100
—
0
120
ns
9 Slave disable time (hold time to high-impedance state)
Data valid
10
Master (before capture edge)
Slave (after enable edge)(3)
tDIS
tV(M)
tV(S)
—
0.25
—
240
ns
—
tCYC(M)
240
ns
Data hold time (outputs)
11
Master (after capture edge)
slave (After Enable Edge)
Rise time (20% VDD to 70% VDD, CL = 200 pF)
12
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
Fall time (70% VDD to 20% VDD, CL = 200 pF)
13
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tHO(M)
tHO(S)
tRM
tRS
tFM
tFS
0.25
0
—
—
—
—
—
tCYC(M)
—
ns
100
ns
2.0
µs
100
ns
2.0
µs
1. VDD = 5.0 Vdc ± 10%; VSS = 0 Vdc, TA = –40 to +85°C, unless otherwise noted. Refer to Figure 12-9 and Figure 12-10.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins.
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
102
Freescale Semiconductor
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