MC68HC705C9A Datasheet, PDF (74/118 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the
transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write
collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF flag of the SPSR
is set.
In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR,
until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of
data and then SCK goes idle again.
In a slave mode, the slave select start logic receives a logic low at the SS pin and a clock at the SCK pin.
Thus, the slave is synchronized with the master. Data from the master is received serially at the MOSI
line and loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred
to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock
train from the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave interconnections.
PD3/MOSI
SPI SHIFT REGISTER
76543210
SPDR ($000C)
PD2/MISO
PD5/SS
I/O PORT
SPI SHIFT REGISTER
76543210
SPDR ($000C)
PD4/SCK
MASTER MCU
SLAVE MCU
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
10.5 SPI Registers
Three registers in the SPI provide control, status, and data storage functions. These registers are called
the serial peripheral control register (SPCR), serial peripheral status register (SPSR), and serial
peripheral data I/O register (SPDR) and are described in the following paragraphs.
10.5.1 Serial Peripheral Control Register
The SPI control register (SPCR), shown in Figure 10-4, controls these functions:
• Enables SPI interrupts
• Enables the SPI system
• Selects between standard CMOS or open drain outputs for port D (C9A mode only)
• Selects between master mode and slave mode
• Controls the clock/data relationship between master and slave
• Determines the idle level of the clock pin
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
74
Freescale Semiconductor