MC68HC705C9A Datasheet, PDF (101/118 Pages) Motorola, Inc – Microcontrollers

(NOTE 1)
V_DD
3.3-Vdc Control Timing
OSC1 PIN⁽²⁾
INTERNAL
CLOCK⁽³⁾
4064 t_CYC
INTERNAL
ADDRESS BUS⁽³⁾
3FFE
3FFE
3FFE
3FFE
3FFE
INTERNAL
DATA BUS⁽³⁾
RESET PIN
(NOTE 4)
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. OSC1 line is meant to represent time only, not frequency.
3. Internal clock, internal address bus, and internal data bus are not available externally.
4. RESET outputs V_OL during 4064 POR cycles.
Figure 12-7. Power-On Reset Timing Diagram
3FFE
3FFF
NEW
NEW
PCH
PCL
INTERNAL
CLOCK⁽¹⁾
INTERNAL
ADDRESS BUS⁽¹⁾
INTERNAL
DATA BUS⁽¹⁾
RESET⁽²⁾
3FFE
3FFE
3FFE
3FFE
3FFF
NEW PC
NEW
NEW
OP
PCH
PCL
CODE
t_RL
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 12-8. External Reset Timing
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
101