MC68HC705C9A Datasheet, PDF (41/118 Pages) Motorola, Inc – Microcontrollers

MC68HC05C9A Compatible COP
5.5 MC68HC05C9A Compatible COP
This COP is controlled with two registers; one to reset the COP timer and the other to enable and control
COP and clock monitor functions. Figure 5-3 shows a block diagram of the MC68HC05C9A COP.
CM1
INTERNAL
CPU
÷4 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
CM0
CLOCK
16 BIT TIMER SYSTEM
2¹⁵
2¹³
2¹⁷
2¹⁹
COP
÷4
÷2 ÷2
÷2 ÷2
÷2 ÷2 ²²¹
COPRST
Figure 5-3. C9A COP Block Diagram
5.5.1 C9A COP Reset Register
This write-only register, shown in Figure 5-4, is used to reset the COP.
$001D Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 5-4. COP Reset Register (COPRST)
The sequence required to reset the COP timer is:
• Write $55 to the COP reset register
• Write $AA to the COP reset register
Both write operations must occur in the order listed, but any number of instructions may be executed
between the two write operations provided that the COP does not time out between the two writes. The
elapsed time between software resets must not be greater than the COP timeout period. If the COP
should time out, a system reset will occur and the device will be re-initialized in the same fashion as a
power-on reset or reset.
Reading this register does not return valid data.
5.5.2 C9A COP Control Register
The COP control register, shown in Figure 5-5, performs these functions:
• Enables clock monitor function
• Enables MC68HC05C9A compatible COP function
• Selects timeout duration of COP timer
and flags the following conditions:
• A COP timeout
• Clock monitor reset
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
41