MC68HC705C9A Datasheet, PDF (69/118 Pages) Motorola, Inc – Microcontrollers

SCI I/O Registers
FE — Receiver Framing Error Flag
This clearable, read-only flag is set when there is a logic 0 where a stop bit should be in the character
shifted into the receive shift register. If the received word causes both a framing error and an overrun
error, the OR flag is set and the FE flag is not set. Clear the FE bit by reading the SCSR and then
reading the SCDR.
1 = Framing error
0 = No framing error
9.13.5 Baud Rate Register
The baud rate register (BAUD), shown in Figure 9-12, selects the baud rate for both the receiver and the
transmitter.
$000D Bit 7
6
5
4
3
Read:
Write:
SCP1
SCP0
Reset: —
—
0
0
—
= Unimplemented
U = Undetermined
2
SCR2
U
1
SCR1
U
Figure 9-12. Baud Rate Register (BAUD)
Bit 0
SCR0
U
SCP1 — SCP0–SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator clock, as shown in Table 9-1. Reset
clears both SCP1 and SCP0.
Table 9-1. Baud Rate Generator Clock Prescaling
SCP[1:0]
00
01
10
11
Baud Rate Generator Clock
Internal Clock ÷ 1
Internal Clock ÷ 3
Internal Clock ÷ 4
Internal Clock ÷ 13
SCR2 — SCR0–SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate, as shown in Table 9-2. Resets have no effect on the
SCR2–SCR0 bits.
Table 9-2. Baud Rate Selection
SCR[2:0]
000
001
010
011
100
101
110
111
SCI Baud Rate (Baud)
Prescaled Clock ÷ 1
Prescaled Clock ÷ 2
Prescaled Clock ÷ 4
Prescaled Clock ÷ 8
Prescaled Clock ÷ 16
Prescaled Clock ÷ 32
Prescaled Clock ÷ 64
Prescaled Clock ÷ 128
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
69