MC68HC705C9A Datasheet, PDF(100/118 Page) Motorola, Inc

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MC68HC705C9A Datasheet, PDF (100/118 Pages) Motorola, Inc – Microcontrollers

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Electrical Specifications

IRQ PIN

tILIL

tILIH

a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz)

or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to

execute the interrupt service routine plus 19 tCYC cycles.

IR.Q1

tILIH

NORMALLY

USED WITH

WIRED-OR

IRQN

CONNECTION

IRQ

(INTERNAL)

b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low,

the next interrupt is recognized

Figure 12-5. External Interrupt Timing

OSC(1)

tRL

RESET

tILIH

IRQ(2)

IRQ(3)

INTERNAL

CLOCK

4064 tCYC

3FFE

3FFF4

Notes:

1. Represents the internal clocking of the OSC1 pin

2. IRQ pin edge-sensitive mask option

3. IRQ pin level- and edge-sensitive mask option

4. RESET vector address shown for timing example

RESET OR INTERRUPT

VECTOR FETCH

Figure 12-6. STOP Recovery Timing Diagram

MC68HC05C9A Advance Information Data Sheet, Rev. 4.1

100

Freescale Semiconductor

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