MC68HC705C9A Datasheet, PDF (16/118 Pages) Motorola, Inc – Microcontrollers

General Description
• The port D data direction register ($0007) is disabled and the seven port D pins become input only.
• SPI output signals (MOSI, MISO, and SCK) do not require the data direction register control for
output capability.
• The port D wire-OR mode control bit (bit 5 of SPCR $000A) is disabled, preventing open-drain
configuration of port D.
• The RESET pin becomes input only.
1.4 Mask Options
The following two mask option registers are used to select features controlled by mask changes on the
MC68HC05C9A and the MC68HC05C12A:
• Port B mask option register (PBMOR)
• C12 mask option register (C12MOR)
The mask option registers are EPROM locations which must be programmed prior to operation of the
microcontroller.
1.4.1 Port B Mask Option Register (PBMOR)
The PBMOR register, shown in Figure 1-2, contains eight programmable bits which determine whether
each port B bit (when in input mode) has the pullup and interrupt enabled. The port B interrupts share the
vector and edge/edge-level sensitivity with the IRQ pin. For more details, (see 4.3 External Interrupt (IRQ
or Port B)).
$3FF0
Bit 7
PBPU7
6
PBPU6
5
PBPU5
4
PBPU4
3
PBPU3
2
PBPU2
Figure 1-2. Port B Mask Option Register
1
PBPU1
Bit 0
PBPU0
PBPU7–PBPU0 — Port B Pullup/Interrupt Enable Bits
1 = Pullup and CPU interrupt enabled
0 = Pullup and CPU interrupt disabled
NOTE
The current capability of the port B pullup devices is equivalent to the
MC68HC05C9A, which is less than the MC68HC05C12A.
1.4.2 C12 Mask Option Register (C12MOR)
The C12MOR register, shown in Figure 1-3, controls the following options:
• Select between MC68HC05C9A/C12A configuration
• Enable/disable stop mode (C12A mode only)
• Enable/disable COP (C12A mode only)
• Edge-triggered only or edge- and level-triggered external interrupt pin (IRQ pin) (C12A mode only).
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
16
Freescale Semiconductor