MC68HC705C9A Datasheet, PDF (73/118 Pages) Motorola, Inc – Microcontrollers

Functional Description
the SPSR. In master mode the SS pin can be selected to be a general-purpose output (when configured
as an MC68HC05C9A) by writing a 1 in bit 5 of the port D data direction register, thus disabling the mode
fault circuit.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high
between successive characters in an SPI message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS line could be tied to V_SS as long as
CPHA = 1 clock modes are used.
10.4 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master device
transmits data to a slave via the MOSI line, the slave device responds by sending data to the master
device via the master’s MISO line. This implies full duplex transmission with both data out and data in
synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and
eliminates the need for separate transmit-empty and receive-full status bits. A single status bit (SPIF) is
used to signify that the I/O operation has been completed.
SPI SHIFT REGISTER
76543210
S
M
PD2/
MISO
M
PD3/
S MOSI
INTERNAL DATA BUS
SPDR ($000C)
INTERNAL
CLOCK
(XTAL ÷2)
SPIE
SPE
MSTR
SPIF
WCOL
MODF
DIVIDER
÷ 2 ÷ 4 ÷ 16 ÷ 32
SPI
CONTROL
SPI INTERRUPT REQUEST
SELECT
SPI CLOCK (MASTER)
SPR1 SPR0
CLOCK
LOGIC
MSTR CPHA CPOL
SPI
CLOCK
(SLAVE)
SPI
CLOCK
(MASTER)
PD5/
SS
PD4/
SCK
SPI CONTROL REGISTER (SPCR)
SPI STATUS REGISTER (SPSR)
SPI DATA REGISTER (SPDR)
7
SPIE
SPIF
BIT 7
6
SPE
WCOL
BIT 6
5
DWOM
0
BIT 5
4
MSTR
MODF
BIT 4
3
CPOL
0
BIT 3
2
CPHA
0
BIT 2
1
SPR1
0
BIT 1
0
SPR2
0
BIT 0
$000A
$000B
$000C
Figure 10-2. Serial Peripheral Interface Block Diagram
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
73