MC68HC705C9A Datasheet, PDF (53/118 Pages) Motorola, Inc – Microcontrollers

8.3.1 Timer Control Register
The timer control register (TCR), shown in Figure 8-2, performs these functions:
• Enables input capture interrupts
• Enables output compare interrupts
• Enables timer overflow interrupts
• Controls the active edge polarity of the TCAP signal
• Controls the active level of the TCMP output
Timer I/O Registers
$0012
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
0
0
0
ICIE
OCIE
TOIE
IEDG
0
0
0
0
0
0
U
= Unimplemented
U = Undetermined
Figure 8-2. Timer Control Register (TCR)
Bit 0
OLVL
0
ICIE — Input Capture Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on the TCAP pin. Resets clear the
ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on the TCMP pin. Resets clear the
OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables interrupts caused by a timer overflow. Reset clear the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Edge Bit
The state of this read/write bit determines whether a positive or negative transition on the TCAP pin
triggers a transfer of the contents of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture
0 = Negative edge (high to low transition) triggers input capture
OLVL — Output Level Bit
The state of this read/write bit determines whether a logic 1 or logic 0 appears on the TCMP pin when
a successful output compare occurs. Resets clear the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
53